`timescale 1ns / 1ps
//Name: Robert Smith
//PID: A08609119
//Name: Shreenidhi Chowkwale
//PID: A09089080

// NUM_REG : number of registers in the register file
// SEL_WIDTH : number of bits needed to specify a register
// D_WIDTH : data width
  
module regfile#(parameter NUM_REG = 16, SEL_WIDTH = 4, D_WIDTH = 34, I_WIDTH = 136)
(
	input  clk,
	input  wen_i,
	input  [I_WIDTH - 1: 0] instr_i,
	input  ldinst_valid_i,
	input  [SEL_WIDTH-1 : 0]  wa_i, // address of register to write to
	input  [D_WIDTH-1 : 0]    wd_i, // data to be written to wa_i register
	input  [SEL_WIDTH-1 : 0]  ra0_i,
	input  [SEL_WIDTH-1 : 0]  ra1_i,
	output [D_WIDTH-1: 0] op_reg_o,
	output [D_WIDTH-1 : 0]    rd0_o,
	output [D_WIDTH-1 : 0]    rd1_o
);

	reg [D_WIDTH - 1 : 0] rf[NUM_REG - 1 : 0];
	
	assign rd0_o = rf[ra0_i];
	assign rd1_o = rf[ra1_i];
	assign op_reg_o = rf[16'b1];
	
	always_ff @(posedge clk)
		begin
			rf[16'b0] = 34'b0;
			if(wen_i)
				begin
					if(ldinst_valid_i)
						begin
							rf[4'b1] = instr_i[I_WIDTH - 1 : I_WIDTH - 34];
							rf[4'b10] = instr_i[I_WIDTH - 35 : I_WIDTH - 68];
							rf[4'b11] = instr_i[I_WIDTH - 69 : I_WIDTH - 102];
							rf[4'b100] = instr_i[I_WIDTH - 103 : I_WIDTH - 136];
						end
					else
						rf[wa_i] = wd_i;
				end
		end
		
endmodule
